Counting Cache errors.
 

Im not sure if C++ is the best, or acceptable language for accomplishing this, but I have encountered a rather steep decrease in performance due to overclocking and would like to see if its due to cache errors.

Some results from benchmarking show that cache latency was greatly increased, cache bandwidth was decreased, and IPS was decreased. There was almost exactly a 50% reduction in MIPS/MHz when overclocking.

Thanks

Wow, way to provide details without getting to the point. Sorry about that. What I am requesting is direction on how to write a program to count cache errors.

Thanks,

What processor are you using?? And I don't think you can do this in C++

Opteron 165.

I doubted C++ would be possible or best for this, but I didnt know which language would be better. Assembly?

Are you talking about on-chip cache or OS cache? Are you overclocking the CPU or just the external busses? If it's the former, I think you're going to have to get intimately familiar with the on-chip circuitry as regards setup and hold times and prop delays. You can probably cool the processor enough to keep the junctions from melting down due to the frequency increase, but you can't make the circuits any faster than they are. You can make them irrecoverably slower than they were with heat stress, if you manage not to melt them.

Im referring to on-chip cache. Im overclocking the CPU, Bus, LDT, and RAM. I closely monitor temps to stay within safe limits, but Im getting better performance at 2.025GHz, even 1.8GHz than I get with 2.41GHz so Im trying to troubleshoot. I believe it has something to do with either the LDT or getting errors in cache as the latency dramatically increased.

Again, even if the temperature is safe, the ability of the devices, timing wise, may be exceeded. Depending on the design, this may result in wait states being introduced, or simply failure to read/write. Clocks and gates are not formed by ideally rectangular pulses. They are trapezoids. The angle is determined by the speed the device can actually achieve. If you increase the frequency, the rise and fall times may preclude the signal from reaching the binary switching threshold before it's time to reverse directions. Errors in data transfer are the result.

Yes, but Ive had the system run stably at 2.7 GHz. I just wasnt happy with the temps or my ability to cool it, so I found a stable profile at 2.4GHz.

Im all for troubleshooting the overclocking problem, but I would appreciate more direction on my original question about cache errors.

Thanks

You're the one with the hardware in hand and, presumably, measuring tools.

Suppose you've overclocked the memory beyond it's ability to respond with zero wait states. Adding one wait state will approximately double the access time. Moving stuff into the cache will therefore take longer.

Suppose you're not meeting the setup and hold times of the memory. The transferred data will be in error.

You're dicking with hardware, not software. Put an analyzer (not cheap) on it or just make some reasonable assumptions and back off on the amount you're souping it up.

You may not realize it, but if you look at the address and data lands connecting to the memory, you may find that they are tuned in length. Possibly little spirals or back and forth zig-zags. This is to reduce degradations caused by reflections. The reflections are caused because the lengths are in the quarter- to half-wavelengh at the frequencies in question, and because of imperfect termination. A good scope will show you a lot of trash which has been minimized by the designer's choices. If you dink with those choices, you need to do so with some understanding. You aren't going to get that depth of understanding with a few forum responses. Get into the hardware.

I dont have a scope to use, nor do I feel like lugging one to campus to use one.

Lets just forget for a bloody moment that I am overclocking. What can I use to make a program to count cache errors?

Thanks