Programming Forums > Application Development > C++

80085 · May 13th, 2005, 4:17 PM

Hi all,

I'm new to this forum and need some help with lex/yacc.

I'm writing a parser that takes a verilog module specification I've developed as an input.

My question might seem relatively simple to this group since my job function is not software development. My main problem is that I can't figure out where to place a sensible boundary between lex and yacc.

The verilog signal specification we've developed can take the form of:

(Toggle Plain Text)

  variable = 0 to 10;
  SIGNAL storage_{variable}_ack[12:0]
  SIGNAL storage_req
  SIGNAL storage_buffer[12:0]

How do I write a lexer that takes into account all of these formats, and more importantly, how do I then store the bit range values and the variable references and associate them with the signal?

For now I've written complex grammar rules in yacc to account for each unique combination:

(Toggle Plain Text)

 
  STRING '[' INT ':' INT ']'
  STRING '{' STRING '}' STRING '[' INT ':' INT ']'

etc etc etc...

It's easy to observe that the grammar rules quickly become unmanageable at some point and that the tool will not scale easily as multiple variables can be referenced...

It seems obvious to me that this bit-range/variable parsing needs to be done initially in the lexer, and then the entire signal structure passed to yacc... I'm just not sure how to do this in lex. This would be a cakewalk in something like PERL, but lex cannot grab "pieces" of a regular expression match... or at least I'm not aware of it.

Can someone help?

Signed,
hardware architect in dire need of good software experience

May 13th, 2005, 4:17 PM	#1
80085 Newbie Join Date: May 2005 Posts: 1 Rep Power: 0	lex/yacc and verilog Hi all, I'm new to this forum and need some help with lex/yacc. I'm writing a parser that takes a verilog module specification I've developed as an input. My question might seem relatively simple to this group since my job function is not software development. My main problem is that I can't figure out where to place a sensible boundary between lex and yacc. The verilog signal specification we've developed can take the form of: (Toggle Plain Text) variable = 0 to 10; SIGNAL storage_{variable}_ack[12:0] SIGNAL storage_req SIGNAL storage_buffer[12:0] variable = 0 to 10; SIGNAL storage_{variable}_ack[12:0] SIGNAL storage_req SIGNAL storage_buffer[12:0] How do I write a lexer that takes into account all of these formats, and more importantly, how do I then store the bit range values and the variable references and associate them with the signal? For now I've written complex grammar rules in yacc to account for each unique combination: (Toggle Plain Text) STRING '[' INT ':' INT ']' STRING '{' STRING '}' STRING '[' INT ':' INT ']' STRING '[' INT ':' INT ']' STRING '{' STRING '}' STRING '[' INT ':' INT ']' etc etc etc... It's easy to observe that the grammar rules quickly become unmanageable at some point and that the tool will not scale easily as multiple variables can be referenced... It seems obvious to me that this bit-range/variable parsing needs to be done initially in the lexer, and then the entire signal structure passed to yacc... I'm just not sure how to do this in lex. This would be a cakewalk in something like PERL, but lex cannot grab "pieces" of a regular expression match... or at least I'm not aware of it. Can someone help? Signed, hardware architect in dire need of good software experience Last edited by big_k105; May 13th, 2005 at 4:45 PM. Reason: fixed code tags :)

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Programming Forums > Application Development > C++

lex/yacc and verilog